Parallel hybrid genetic algorithms on consumer-level graphics hardware

Document Type

Conference paper

Source Publication

Proceedings of the 2006 IEEE Congress on Evolutionary Computation, CEC 2006

Publication Date

1-1-2006

First Page

2973

Last Page

2980

Publisher

Institute of Electrical and Electronics Engineers

Abstract

In this paper, we report a parallel Hybrid Genetic Algorithm (HGA) on consumer-level graphics cards. HGA extends the classical genetic algorithm by incorporating the Cauchy mutation operator from evolutionary programming. In our parallel HGA, all steps except the random number generation procedure are performed in Graphics Processing Unit (GPU) and thus our parallel HGA can be executed effectively and efficiently. We propose the pseudo-deterministic selection method which is comparable to the traditional global selection approach with significant execution time performance advantages. We perform experiments to compare our parallel HGA with our previous parallel FEP (Fast Evolutionary programming) and demonstrate that the former is much more effective and efficient than the latter. The parallel and sequential implementations of HGA are compared in a number of experiments, it is observed that the former outperforms the latter significantly. The effectiveness and efficiency of the pseudodeterministic selection method is also studied.

DOI

10.1109/CEC.2006.1688683

Publisher Statement

Copyright © 2006 IEEE. Access to external full text or publisher's version may require subscription.

Additional Information

Paper presented at the 2006 IEEE Congress on Evolutionary Computation (CEC 2006), 16-21 July 2006, Vancouver, Canada.

ISBN of the source publication: 9780780394872

Full-text Version

Publisher’s Version

Language

English

Recommended Citation

Wong, M.-L., & Wong, T.-T. (2006). Parallel hybrid genetic algorithms on consumer-level graphics hardware. In Proceedings of the 2006 IEEE Congress on Evolutionary Computation, CEC 2006 (pp. 2973-2980). Piscataway: Institute of Electrical and Electronics Engineers. doi: 10.1109/CEC.2006.1688683

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