Title

Formal verification of fault-tolerant software design : the CSP approach

Document Type

Journal article

Source Publication

Microprocessors & Microsystems

Publication Date

6-1-2005

Volume

29

Issue

5

First Page

197

Last Page

209

Abstract

Software design techniques for tolerating both hardware and software faults have been developed over the past few decades. Paradoxically, it is essential that fault-tolerant software is designed with the highest possible rigour to prevent faults in itself. Such rigour is provided by formal methods and aided by model checking. We illustrate an approach to fault-tolerant software design based on communicating sequential processes through a running example.

DOI

10.1016/j.micpro.2004.07.005

Print ISSN

01419331

E-ISSN

18729436

Publisher Statement

Copyright © 2004 Elsevier B.V.

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Full-text Version

Publisher’s Version

Recommended Citation

Yeung, W. L., & Schneider, S. A. (2005). Formal verification of fault-tolerant software design: The CSP approach. Microprocessors & Microsystems, 29(5), 197-209. doi: 10.1016/j.micpro.2004.07.005